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8902-A
3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING
LOAD SUPPLY C D2 C WD CST OUTA GROUND GROUND OUT B OUT C CENTERTAP BRAKE C RES 1 2 V BB COMMUTATION DELAY 24 23 C D1 DATA IN CLOCK CHIP SELECT RESET GROUND GROUND DATA OUT OSCILLATOR LOGIC SUPPLY SECTOR DATA FILTER
Data Sheet 26301.2
SERIAL PORT
3 4 5 6 7 8 9 9 10 11 12 BOOST CHARGE PUMP
22 21 20 19 18
The A8902CLBA is a three-phase brushless dc motor controller/ driver for use in 5 V or 12 V hard-disk drives. The three half-bridge outputs are low on-resistance n-channel DMOS devices capable of driving up to 1.25 A. The A8902CLBA provides complete, reliable, self-contained back-EMF sensing motor startup and running algorithms. A programmable digital frequency-locked loop speed control circuit together with the linear current control circuitry provides precise motor speed regulation. A serial port allows the user to program various features and modes of operation, such as the speed control parameters, startup current limit, sleep mode, diagnostic modes, and others. The A8902CLBA is fabricated in Allegro's BCD (Bipolar CMOS DMOS) process, an advanced mixed-signal technology that combines bipolar, analog and digital CMOS, and DMOS power devices. The A8902CLBA is provided in a 24-lead wide-body SOIC batwing package. It provides for the smallest possible construction in surface-mount applications.
MUX FLL VDD
17 16 15 14 13
Dwg. PP-040B
FEATURES
s s s s s s s s s s s s s s s s s DMOS Outputs Low rDS(on) Startup Commutation Circuitry Back-EMF Commutation Circuitry Serial Port Interface Frequency-Locked Loop Speed Control Sector Data Tachometer Signal Input Programmable Start-Up Current Diagnostics Mode Sleep Mode Linear Current Control Internal Current Sensing Dynamic Braking Through Serial Port Power-Down Dynamic Braking System Diagnostics Data Out Data Out Ported in Real Time Internal Thermal Shutdown Circuitry
ABSOLUTE MAXIMUM RATINGS
at TA = +25C
Load Supply Voltage, VBB . . . . . . . . . . 14 V Output Current, IOUT . . . . . . . . . . . . 1.25 A Logic Supply Voltage, VDD . . . . . . . . . 6.0 V Logic Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Package Power Dissipation, PD See Graph Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . 0C to +70C Junction Temperature, TJ . . . . . . . +150C Storage Temperature Range, TS . . . . . . . . . . . . . . . -55C to +150C
Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided. Output current rating may be restricted to a value determined by system concerns and factors. These include: system duty cycle and timing, ambient temperature, and use of any heatsinking and/or forced cooling. For reliable operation, the specified maximum junction temperature should not be exceeded.
Always order by complete part number, e.g., A8902CLBA .
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
FUNCTIONAL BLOCK DIAGRAM
LOGIC SUPPLY
15
C D1
24
C D2
2
C ST
4
BRAKE
11
C RES
12
VDD BOOST CHARGE PUMP
1
BRAKE
VBB
LOAD SUPPLY OUT A OUT B OUTC
COMMUTATION LOGIC
OUT A OUT B OUT C CENTERTAP C WD
10
START-UP OSC. BLANK
SEQUENCE LOGIC
FCOM COMMUTATION DELAY
5
8
9
3
WATCHDOG TIMER
SECTOR 14 DATA OSC 16 FREQUENCYLOCKED LOOP CHARGE PUMP CURRENT CONTROL RS
6-7
GROUND
DATA IN
23
SERIAL PORT
MUX
TSD
18-19
GROUND
21
22
20
17
13
CHIP SELECT
CLOCK
RESET
DATA OUT
FILTER
Dwg. FP-034
ALLOWABLE PACKAGE POWER DISSIPATION in WATTS
2.5
RJT = 6C/W
2.0
1.5
1.0
R JA = 55C/W
0.5
0 25 50 75 100 125 150
Dwg. GP-019B
TEMPERATURE in C
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1992, 1995 Allegro MicroSystems, Inc.
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25C, VDD = 5.0 V
Limits Characteristic Logic Supply Voltage Logic Supply Current Symbol VDD IDD Operating Operating Sleep Mode Load Supply Voltage Thermal Shutdown Thermal Shutdown Hysteresis Output Drivers Output Leakage Current IDSX VBB = 14 V, VOUT = 14 V VBB = 14 V, VOUT = 0 V Total Output ON Resistance (Source + Sink + RS) Output Sustaining Voltage Clamp Diode Forward Voltage Control Logic Logic Input Voltage VIN(0) VIN(1) Logic Input Current IIN(0) IIN(1) DATA Output Voltage VOUT(0) VOUT(1) CST Current ICST SECTOR DATA, RESET, CLK, CHIP SELECT, OSC VIN = 0 V VIN = 5.0 V IOUT = 500 A IOUT = -500 A Charging Discharging CST Threshold VCSTH VCSTL Filter Current IFILTER Charging Discharging Leakage, VFILTER = 2.5 V Filter Threshold CD Current (CD1 or CD2) CD Current Matching CD Threshold -- VCDTH VFILTERTH ICD Charging Discharging ICD(DISCHRG)/ICD(CHRG) -0.3 3.5 -- -- -- 3.5 -9.0 -- 2.25 0.85 -9.0 9.0 -- 1.57 -18 32 1.8 2.25 -- -- -- -- -- -- -10 500 2.5 1.0 -10 10 -- 1.85 -20 40 2.0 2.5 1.5 5.3 -0.5 1.0 1.5 -- -11 -- 2.75 1.15 -11 11 5.0 2.13 -22 48 2.2 2.75 V V A A V V A A V V A A nA V A A -- V rDS(on) IOUT = 600 mA -- -- -- 1.0 -1.0 1.0 300 -300 1.4 A A VBB TJ TJ Operating Test Conditions Min. 4.5 -- -- 4.0 -- -- Typ. 5.0 7.5 250 -- 165 20 Max. 5.5 10 500 14 -- -- Units V mA A V C C
VDS(sus) VF
VBB = 14 V, IOUT = IOUT(MAX), L = 3 mH IF = 1.0 A
14 --
-- 1.25
-- 1.5
V V
Continued next page ...
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
ELECTRICAL CHARACTERISTICS continued
Limits Characteristic CWD Current CWD Threshold Voltage Symbol ICWD VTL VTH Max. FLL Oscillator Frequency IOUT(MAX) fOSC -- VDD = 5.0 V, TA = 25C D3 = 0, D4 = 0 D3 = 0, D4 = 1 D3 = 1, D4 = 0 D3 = 1, D4 = 1 BRAKE Threshold BRAKE Hysteresis Current Transconductance Gain Centertap Resistors Back-EMF Hysteresis VBRK IBRKL gm RCT -- VBEMF - VCTAP at FCOM Transition VBRK = 750 mV Charging Test Conditions Min. -9.0 0.22 2.25 12 1.0 0.9 0.5 -- 1.5 -- 0.42 5.0 5.0 -5.0 Typ. -10 0.25 2.5 -- 1.2 1.0 0.6 250 1.75 20 0.50 10 20 -20 Max. -11 0.28 2.75 -- 1.4 1.1 0.7 -- 2.0 -- 0.58 13 37 -37 Units A V V MHz A A A mA V A A/V k mV mV
SERIAL PORT TIMING CONDITIONS
CHIP SELECT E CLOCK C DATA D C D A B
Dwg. WP-019
A. Minimum CHIP SELECT setup time before CLOCK rising edge .......... 100 ns B. Minimum CHIP SELECT hold time after CLOCK rising edge ............... 150 ns C. Minimum DATA setup time before CLOCK rising edge ........................ 150 ns D. Minimum DATA hold time after CLOCK rising edge ............................. 150 ns E. Minimum CLOCK low time before CHIP SELECT .................................. 50 ns F. Maximum CLOCK frequency .............................................................. 3.3 MHz
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
TERMINAL FUNCTIONS
Term. 1 2 3 4 5 6-7 8 9 10 11 Terminal Name LOAD SUPPLY CD2 CWD CST OUTA GROUND OUTB OUTC CENTERTAP BRAKE Function VBB; the 5 V or 12 V motor supply. One of two capacitors used to generate the ideal commutation points from the back-EMF zero crossing points. Timing capacitor used by the watchdog circuit to disable the back-EMF comparators during commutation transients, and to detect incorrect motor position. Startup oscillator timing capacitor. Power amplifier A output to motor. Power and logic ground and thermal heat sink. Power amplifier B output to motor. Power amplifier C output to motor. Motor centertap connection for back-EMF detection circuitry. Active low turns ON all three sink drivers shorting the motor windings to ground. External capacitor and resistor at BRAKE provide brake delay. The brake function can also be controlled via the serial port. External reservoir capacitor used to hold charge to drive the source drivers' gates. Also provides power for brake circuit. Analog voltage input to control motor current. Also, compensation node for internal speed control loop. External tachometer input. Can use sector or index pulses from disk to provide precise motor speed feedback to internal frequency-locked loop. VDD; the 5 V logic supply. Clock input for the speed reference counter. Typical max. frequency is 10 MHz. Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real time, controlled by 2-bit multiplexer in serial port. Power and logic ground and thermal heat sink. When pulled low forces the chip into sleep mode; clears all serial port bits. Strobe input (active low) for data word. Clock input for serial port. Sequential data input for the serial port. One of two capacitors used to generate the ideal commutation points from the back-EMF zero crossing points.
12 13 14 15 16 17 18-19 20 21 22 23 24
CRES FILTER SECTOR DATA LOGIC SUPPLY OSCILLATOR DATA OUT GROUND RESET CHIP SELECT CLOCK DATA IN CD1
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
FUNCTIONAL DESCRIPTION
Power Outputs. The power outputs of the A8902CLBA are n-channel DMOS transistors with a total source plus sink rDS(on) of typically 1 . Internal charge pump boost circuitry provides voltage above supply for driving the high-side DMOS gates. Intrinsic ground clamp and flyback diodes provide protection when switching inductive loads and may be used to rectify motor back-EMF in power-down conditions. An external Schottky power diode or pass FET is required in series with the load supply to allow motor back-EMF rectification in power down conditions. Back-EMF Sensing Motor Startup and Running Algorithm. The A8902CLBA provides a complete self-contained back-EMF sensing startup and running commutation scheme. The three half-bridge outputs are controlled by a state machine. There are six possible combinations. In each state, one output is high (sourcing current), one low (sinking current), and one is OFF (high impedance or `Z'). Motor back EMF is sensed at the OFF output. The truth table for the output drivers sequencing is:
Sequencer State 1 2 3 4 5 6
backward, or remain stationary (if in a null-torque position). If the motor moves, the back-EMF detection circuit waits for the correct polarity back-EMF zero crossing (output crossing through centertap). True back-EMF zero crossings are used by the adaptive commutation delay circuit to advance the state sequencer (commutate) at the proper time to synchronously run the motor. Back-EMF zero crossings are indicated by FCOM, an internal signal that toggles at every zero crossing. FCOM is available at the DATA OUT terminal via the programmable data out multiplexer.
V
OUTA
V
OUTB
SOURCE ON
BACK-EMF VOLTAGE
V
OUTC
SINK ON
V
CTAP
FCOM TOGGLES AT BACK-EMF ZERO CROSSING
FCOM
Dwg. WP-016-1
OUTA High Z Low Low Z High
OUTB Low Low Z High High Z
OUTC Z High High Z Low Low
Startup Oscillator. If the motor does not move at the initial startup state, then it is in a null-torque position. In this case, the outputs are commutated automatically by the startup oscillator after a period set by the external capacitor at CST where tCST = 4(VCSTH - VCSTL) x CST IST(charge) + IST(discharge)
At startup, the outputs are enabled in one of the sequencer states shown. The back EMF is examined at the OFF output by comparing the output voltage to the motor centertap voltage at CENTERTAP. The motor will then either step forward, step
In the next state, the motor will move, back EMF will be detected, and the motor will accelerate synchronously. Once normal synchronous back-EMF commutation occurs, the startup oscillator is defeated by pulses of pulldown current at CST at each commutation, which prevents CST from reaching its upper threshold and thus completing a cycle and commutating.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
Adaptive Commutation Delay. The adaptive commutation delay circuit uses the back-EMF zero-crossing indicator signal (FCOM) to determine an optimal commutation time for efficient synchronous operation. This circuit commutates the outputs, delayed from the last zero crossing, using two external timing capacitors, CD1 and CD2,
t FCOM FCOM
Blanking and Watchdog Timing Functions. The blanking and watchdog timing functions are derived from one timing capacitor, CWD. VTL x CWD where tBLANK = ICWD and tWD = VTH x CWD ICWD
The CWD capacitor begins charging at each commutation, initiating the BLANK signal. BLANK is an internal signal that inhibits the backEMF comparators during the commutation transients, preventing errors due to inductive recovery and voltage settling transients. The watchdog timing function allows time to detect correct motor position by checking the back-EMF polarity after each commutation. If the correct polarity is not observed between tBLANK and tWD, then the watchdog timer commutates the outputs to the next state to synchronize the motor. This function is useful in preventing excessive reverse rotation, and helps in resynchronizing (or starting) with a moving spindle.
t CD2
V TL
VCWD
tCD1
VCD1
VCD2
V CWD t BLANK BLANK
Dwg. WP-016-2
Dwg. WP-022
to measure the time between crossings. ICD(charge) where tCD = tFCOM x ICD(discharge) CD1 charges up with a fixed current from its 2.5 V reference while FCOM is high. When FCOM goes low at the next zero crossing, CD1 is discharged at approximately twice the charging current. When CD1 reaches the CD threshold, a commutation occurs. CD2 operates similarly except on the opposite phase of FCOM . Thus the commutations occur approximately halfway between zero crossings. The actual delay is slightly less than halfway to compensate for electrical delays in the motor, which improves efficiency.
NORMAL COMMUTATION
VTH
V CWD t BLANK BLANK
V TL
t WD
Dwg. WP-021
WATCHDOG-TRIGGERED COMMUTATION
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
Current Control. The A8902CLBA provides linear current control via the FILTER terminal, an analog voltage input. Maximum current limit is also provided, and is controlled in four steps via the serial port. Output current is sensed via an internal sense resistor (RS). The voltage across the sense resistor is compared to one-tenth the voltage at the FILTER terminal less the filter threshold voltage, or to the maximum current limit reference, whichever is lower. This transconductance function is IOUT = (VFILTER -VFILTERTH) / 10RS, where RS is nominally 0.2 and VFILTERTH is approximately 1.85 V.
YANK POWER UP ERROR FAST FROM FLL V DD S R SPEED-CONTROL INITIALIZATION V DD Ic FILTER C F1 Id /10 C RES VBB BOOST CHARGE PUMP OUT MUX Q SEQUENTIAL LOGIC
60 x fOSC desired = total count desired motor speed (rpm) where the total count (number of oscillator cycles) is equal to the sum of the selected (programmed low) count numbers corresponding to bits D5 through D18. The speed error is detected as the difference in falling edges of TACH and REF. The speed error signals control the error-correcting charge pump on the FILTER terminal, which drive the external loop compensation components to correct the motor current. Sector Mode. An external tachometer signal, such as sector or index pulses, may be used to create the TACH signal, rather than the internally derived once around. To use this mode, the signal is input to the SECTOR terminal, and the sector mode must be enabled via the serial port. When Switching from the once-around mode to sector mode, it is important to monitor the SYNC signal on DATA OUT, and switch modes only when SYNC is low. This ensures making the transition without disturbing the speed control loop. The speed reference counter should be reprogrammed at the same time. Speed Loop Initialization (YANK). To improve the acquire time of the speed control loop, there is an automatic feature controlled by an internal YANK signal. The motor is started at the maximized programmed current by bypassing the FILTER terminal. The FILTER terminal is clamped to an internal reference (the filter threshold voltage), initializing it near the closed loop operating point. YANK is enabled at startup and stays high until the desired speed is reached. Once the first error-fast occurs, indicating the motor crossed through the desired speed, YANK goes low. This releases the clamp on the FILTER terminal and current control is returned to FILTER. This feature optimizes speed acquire and minimizes settling. The Current Control Block Diagram illustrates the YANK signal and its effects.
ERROR SLOW FROM FLL
x1
VI max
- +
LINEAR CURRENT CONTROL RS
C RF1
F2
1.85 V
CHARGE PUMP
FROM SERIAL PORT REGISTER D3 AND D4 ERROR FAST FROM FLL MAX CURRENT LIMIT
Dwg. EP-046
Speed Control. The A8902CLBA includes a frequency-locked loop speed control system. This system monitors motor speed via internal or external digital tachometer signals, generates a precision speed reference, determines the digital speed error, and corrects the motor current via an internal charge pump and external filtering components on the FILTER terminal. A once per revolution TACH signal can be generated by counting cycles of FCOM (the number of motor poles must be selected via the serial port). TACH is then a jitter-free signal that toggles once per motor revolution. The rising edge of TACH triggers REF, a precision speed reference derived by a programmable counter. The duration of REF is set by programming the counter to count the desired number of OSC cycles
SECTOR COUNT (3 x MOTOR POLES) D20 & D21 ONCE-AROUND PULSE D19 REF TACH SERIAL PORT REGISTER D5-D18 REF OSC 4-BIT FIXED COUNTER 14-BIT PROGRAMMABLE COUNTER TACH REF ERROR FAST
Dwg. EP-045
FCOM
MUX
/2
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
+ -
TACH ERROR SLOW
+ -
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
Serial Port. The serial port functions to write various operational and diagnostic modes to the A8902CLBA. The serial port DATA IN is enabled/disabled by the CHIP SELECT terminal. When CHIP SELECT is high the serial port is disabled and the chip is not affected by changes in data at the DATA IN or CLOCK terminals. To write data to the serial port, the CLOCK terminal should be low prior to the CHIP SELECT terminal going low. Once CHIP SELECT goes low, information on the DATA IN terminal is read into the shift register on the positive-going transition of the CLOCK. There are 24 bits in the serial input port. Data written into the serial port is latched and becomes active upon the low-to-high transition of the CHIP SELECT terminal at the end of the write cycle. D0 will be the last bit written to the serial port. Bit Number D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 Count Number 16 32 64 128 256 512 1 024 2 048 4 096 8 192 16 384 32 768 65 536 131 072
SERIAL PORT BIT DEFINITIONS
D0- Sleep/Run Mode; LOW = Sleep, HIGH = Run This bit allows the device to be powered down when not in use. D1- Step Mode; LOW = Normal Operation, HIGH = Step Only When in the step-only mode the back-EMF commutation circuitry is disabled and the power outputs are commutated by the startup oscillator. This mode is intended for device and system testing. D2- Brake; LOW = Run, HIGH = Brake. D3 and D4 - These two bits set the output current limit: D3 0 0 1 1 D4 0 1 0 1 Current Limit 1.2 A 1A 600 mA 250 mA
REF
D19-Speed-control mode switch; LOW = internal once-around speed signal, HIGH = external sector data. D20 and D21-These bits program the number of motor poles for the once-around FCOM counter: D20 0 0 1 1 D21 0 1 0 1 Motor Poles 8 - 16 12
D22 and D23-Controls the multiplexer for DATA OUT: time to set D22 0 0 1 1 D23 0 1 0 1 DATA OUT TACH (once around or sector) Thermal Shutdown SYNC FCOM
D5 thru D18-This 14-bit word (active low) programs the desired motor speed.
Reset. The RESET terminal when pulled low clears all serial port bits, including the D0 latch, which puts the A8902CLBA in the sleep mode.
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
FAULT CB R B
BRAKE
V FAULT
- VD
BRAKE ACTIVATED VBRK t BRK
Dwg. OP-004
brake is activated. Once the brake is activated, due to the inherent capacitive input, the three sink drivers will remain active until the device is reset. tBRK = RBCB 1 - ln VBRK VFAULT - VD
Braking. A dynamic braking feature of the A8902CLBA shorts the three motor windings to ground. This is accomplished by turning the three source drivers OFF and the three sink drivers ON. Activation of the brake can be implemented through the BRAKE input or through the D2 bit in the serial port. The supply voltage for the brake circuitry is the CRES voltage, allowing the brake function to remain active after power failure. Power-down braking with delay can be implemented by using an external RC and other components to control the brake terminal, as shown. Brake delay can be set using the equation below to ensure that voice-coil head retract occurs before the spindle motor
Centertap. The A8902CLBA internally simulates the centertap voltage of the motor. To obtain reliable start-up performance from motor to motor, the motor centertap should be connected to this terminal. External Component Selection. Applications information regarding the selection of external component values is available from the factory for external component selection, frequency-locked loop speed control, and commutation delay capacitor selection.
TYPICAL APPLICATION
V BYPASS COMMUTATION DELAY 24 23
SERIAL PORT
BB
VRET C D2 CWD C ST
1 2 3 4 5 6 7 8 9 9 10
VBB
CD1 DATA IN CLOCK CHIP SELECT RESET
22 21 20 19 18
BYPASS MUX FLL VDD BOOST CHARGE PUMP 17 16 15 14 13 CF2
Dwg. EP-036C
DATA OUT OSC (REF) +5 V R F1 SECTOR DATA CF1
FAULT RB
CB
11 12
CRES 0.22 F
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
Dimensions in Inches (for reference only)
24
13
0.0125 0.0091
0.2992 0.2914
0.491 0.394 0.050 0.016
0.020 0.013
1
2
3
0.6141 0.5985
0.050
BSC NOTE 1 NOTE 3
0 TO 8
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-25 in
Dimensions in Millimeters (controlling dimensions)
24
13
0.32 0.23
7.60 7.40
10.65 10.00 1.27 0.40
0.51 0.33
1
2
3
15.60 15.20
1.27
BSC NOTE 1 NOTE 3
0 TO 8
2.65 2.35 0.10 MIN.
Dwg. MA-008-25A mm
NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor's option within limits shown.
8902-A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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